The present invention relates to an improved successive approximation register analog to digital converter (SAR ADC) and particularly, to an SAR ADC having increase immunity to time variant noise signals on its reference voltage sources.
SAR ADCs are well known devices. Generally, they generate a digital code representing the magnitude of an input voltage (VIN). SAR ADCs operate in two phases—a sampling phase and a bit trial phase. During the sampling phase, the input voltage is acquired. During the bit trial phase, the input voltage is compared against test voltages to determine whether the input voltage is greater than or less than the respective test voltages. SAR ADCs operate bit by bit, comparing the input voltage initially to an analog voltage value corresponding to the most significant bit (MSB), deciding upon the value of the MSB and thereafter comparing the input voltage to an analog voltage value representing a combination of the selected MSB and a candidate value for the next lower bit position. The bit trial process operates incrementally across all bit positions from the MSB to the least significant bit (LSB) position until a complete digital code is generated that corresponds to the input voltage.
SAR ADCs, however, suffer from noise effects that may be present in source voltages that are used by the circuit. Often, the SAR ADC uses a voltage source VREF representing the highest voltage that the input voltage can take. The SAR ADC may use another reference voltage VREF that is maintained either at VDD or at some intermediate potential. In modern circuit systems, both of the voltage sources can include time-varying noise components that can introduce error to the conversion process.
FIGS. 1(a) and 1(b) illustrate a SAR ADC 100 that suffers from such noise effects. Here, the ADC 100 includes two arrays of capacitors 110, 120, called “PDAC” and “NDAC” respectively, that are coupled to positive and negative inputs of a differential comparator 130. The PDAC 110 includes an array of binary weighted capacitors 112.1-112.n and a coupling capacitor 114. The coupling capacitor 114 divides the PDAC 110 into two spans 114.1 and 114.2. Bottom plates of each capacitor 112.1-112.n in the first span 114.1 are coupled to switches 116.1-116.7 which can be selectively controlled to couple the bottom plates respectively to VIN, VREF or ground by a control signal (not shown). Bottom plates of remaining capacitors are selectively connected by switches 116.8-116.n to VREF and ground. Top plates of all capacitors 112.1-112.7 in the main DAC span 114.1 and the coupling capacitor 114 are coupled to switches (shown collectively as 118), which permit the capacitors to be selectively coupled to VDD, VSS (ground) and the positive terminal of the differential comparator 130. Top plates of the remaining capacitors 112.8-112.n are coupled to the coupling capacitor 114.
The NDAC 120 also includes an array of binary weighted capacitors 122.1-122.n and a coupling capacitor 124. Bottom plates of each capacitor 122.1-122.n are coupled to switches 126.1-126.n which selectively couple the bottom plates to VREF or ground by a control signal (not shown). Top plates of all capacitors 122.1-122.7 of a main DAC span 124.1 and the coupling capacitor 124 are coupled to switches (shown collectively as 128), which permit the capacitors to be selectively coupled to VDD, VSS and the negative terminal of the differential comparator 130. Top plates of the remaining capacitors 122.8-122.n may be coupled to the coupling capacitor 124.
FIG. 1(a) illustrates a switching configuration of the SAR ADC 100 during a sampling phase. Within the PDAC 110, bottom plates of all capacitors within the main DAC span 114.1 are connected to the input voltage VIN. The top plate of the MSB capacitor 112.1 is connected to VSS. Top plates of all other capacitors in the main DAC span 114.1 are connected to VDD. Top plates of the capacitors 112.8-112.n in the sub DAC span 114.2 are connected to ground. Within the NDAC, bottom plates of all capacitors 121.1-121.n and 124 are connected to VSS. A top plate of capacitor 122.1 is connected to VSS and top plates of the other capacitors 122.2-122.7 are connected to VDD. The switch configurations generate four independent nodes, labeled A-D in FIG. 1(a), which carry charges as follows:
TABLE 1NODECHARGEAQA = −VIN * 64CBQB = (VDD − VIN) * (64 + k) * CCQC = 0DQD = VDD(64 + k)Cwhere C represents a capacitance value of a base capacitor 112.n and k represents an aggregate capacitance of the coupling capacitor 114 and the capacitors 112.8-112.n of the sub DAC span 114.2 of the PDAC 110 (or, equivalently, those capacitors of the NDAC).
FIG. 1(b) illustrates a switching configuration of the SAR ADC 100 during a bit trial phase when the MSB position is subject to test. Within the PDAC 110, switches 118 connect nodes A and B to the positive input terminal of the differential comparator 130. Switch 116.1 connects the bottom plate of the MSB capacitor 112.1 to a VREF input and the switches 116.2-116.n connect the bottom plates of the remaining capacitors 112.2-112.n to ground. Within the NDAC 120, switches 128 connect nodes C and D both to the negative input terminal of the differential comparator 130. Switches 126.1-126.n connect all capacitors to ground. The switch configurations generate charges at the input terminals of the differential comparator 130 as follows:
TABLE 2NODECHARGEPositive InputQ = (Vpos − VREF) 64C + (Vpos) * (64 + k)CTerminalNegative InputQneg = (Vneg − 0) (128 + k)CTerminalBecause the charges at the comparator's input terminals are the same as the summation of charges respectively on the node pairs A|B and C|D, the voltages at the positive and negative input terminals (VPOS & VNEG) can be computed as follows:
            V      pos        =                  128                  128          +          k                    [                                                  V              DD                        ⁡                          (                              64                +                k                            )                                128                +                              V            REF                    2                -                  V          in                    ]                  V      neg        =                  128                  128          +          k                    [                                    V            DD                    ⁡                      (                          64              +              k                        )                          128            ]      The voltages at the positive input node has a VREF component, which because VREF is connected during the bit trial phase, can introduce a portion of time varying noise present on VREF to the positive input of the comparator. This noise component of the VREF signal can contributes to ADC conversion error.
Accordingly, there is a need in the art for an improved SAR ADC that provides improved immunity to noise signals present on the voltage sources on which the SAR ADC operates.